View MC10E211FN_742212.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:6 Differential Clock Distribution Chip
The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal (PECL is an acronym for Positive ECL, PECL levels are ECL levels referenced to +5V rather than ground). If a single-ended input is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB supply is designed to act as the switching reference for the input of the E211 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.
MC10E211 MC100E211
1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
* * * * * * * *
Guaranteed Low Skew Specification Synchronous Enabling/Disabling Multiplexed Clock Inputs VBB Output for Single-Ended Use Internal 75k Input Pulldown Resistors Common and Individual Enable/Disable Control High Bandwidth Output Transistors Extended 100E VEE Range of -4.2V to -5.46V
FN SUFFIX PLASTIC PACKAGE CASE 776-02
The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open in which case it will be pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all associated specifications are referenced to the negative edge of the CLK input. The output transitions of the E211 are faster than the standard ECLinPSTM edge rates. This feature provides a means of distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the recommended termination schemes please refer to the applications information section of this data sheet. FUNCTION TABLE
CLK H/L X Z* SCLK X H/L Z* SEL L H X ENx L L H Q CLK SCLK L
* Z = Negative transition of CLK or SCLK
ECLinPS is a trademark of Motorola Inc.
5/95
(c) Motorola, Inc. 1996
2-1
REV 3
MC10E211 MC100E211
EN4 25 EN3 SEL SCLK VEE CLK CLK VBB 26 27 28 1 2 3 4 5 CEN
EN5 24
VCC0 23
Q5 22
Q5 21
Q4 20
Q4 19 18 17 16 15 14 13 12 Q3 Q3 VCC Q2 Q2 Q1 Q1
6 EN2
7 EN1
8 EN0
9 VCC0
10 Q0
11 Q0
Pinout: 28-Lead PLCC (Top View)
Q0 Q0 EN0 DQ
CLK CLK SCLK SEL EN1-4 CEN
BITS 1-4 0 1 DQ Q1-4 Q1-4
Q5 Q5 EN5 DQ
VBB
Logic Diagram
MOTOROLA
2-2
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E211 MC100E211
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C Characteristic Output Reference Voltage 10E 100E Input High Current Power Supply Current 10E 100E Symbol VBB -1.38 -1.38 IIH IEE 119 119 160 160 119 119 160 160 119 137 160 164 -1.27 -1.26 150 -1.35 -1.38 -1.25 -1.26 150 -1.31 -1.38 -1.19 -1.26 150 A mA Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit V Condition
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C Characteristic Propagation Delay to Output CLK to Q (Diff) CLK to Q (SE) SCLK to Q SEL to Q Disable Time CLK or SCLK to Q Part-to-Part Skew CLK (Diff) to Q CLK (SE), SCLK to Q Within-Device Skew Setup Time ENx to CLK CEN to CLK Hold Time CLK to ENx, CEN Minimum Input Swing (CLK) Com. Mode Range (CLK) Rise/Fall Times 20 - 80% 1. 2. 3. 4. Symbol tPLH tPHL Min 795 745 650 745 Typ 930 930 900 970 600 tskew 270 370 75 200 200 900 1.0 Note 0.25 -0.4 270 370 75 200 200 900 1.0 Note 0.25 -0.4 -100 0 ps 900 VPP VCMR 0.25 -0.4 600 160 600 1.0 Note V V 2 3 4 270 370 75 ps 200 200 th -100 0 -100 0 2 Max 1065 1115 1085 1195 800 Min 805 755 650 755 25C Typ 940 940 910 980 600 Max 1075 1125 1095 1205 800 Min 825 775 650 775 85C Typ 960 960 930 1000 600 Max 1095 1145 1115 1225 ps 800 ps 2 Unit ps Condition
tPHL
50 ts
50
1
tr ps tf 150 400 150 400 150 400 Within-Device skew is defined for identical transitions on similar paths through a device. Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings. The range in which the high level of the input swing must fall while meeting the VPP spec. The lower end of the range is VEE dependent and can be calculated as VEE + 2.4V.
ECLinPS and ECLinPS Lite DL140 -- Rev 4
2-3
MOTOROLA
MC10E211 MC100E211
APPLICATIONS INFORMATION
General Description The MC10E/100E211 is a 1:6 fanout tree designed explicitly for low skew high speed clock distribution. The device was targeted to work in conjunction with the E111 device to provide another level of flexibility in the design and implementation of clock distribution trees. The individual synchronous enable controls and multiplexed clock inputs make the device ideal as the first level distribution unit in a distribution tree. The device provides the ability to distribute a lower speed scan or test clock along with the high speed system clock to ease the design of system diagnostics and self test procedures. The individual enables could be used to allow for the disabling of individual cards on a backplane in fault tolerant designs. Because of lower fanout and larger skews the E211 will not likely be used as an alternative to the E111 for the bulk of the clock fanout generation. Figure 1 shows a typical application combining the two devices to take advantage of the strengths of each.
E111 Q0
under worst case VCC situations between cards there will be no AC performance or noise margin loss for the differential CLK inputs. For situations where TTL clocks are required the E211 can be interfaced with the H641 or H643 ECL to TTL Clock Distribution Chips from Motorola. The H641 is a single supply 1:9 PECL to TTL device while the H643 is a 1:8 dual supply standard ECL to TTL device. By combining the superior skew performance of the E211, or E111, with the low skew translating capabilities of the H641 and H643 very low skew TTL clock distribution networks can be realized. Handling Open Inputs and Outputs All of the input pins of the E211 have a 50k to 75k pulldown resistor to pull the input to VEE when left open. This feature can cause a problem if the differential clock inputs are left open as the input gate current source transistor will become saturated. Under these conditions the outputs of the CLK input buffer will go to an undefined state. It is recommended, if possible,that the SCLK input should be selected any time the differential CLK inputs are allowed to float. The SCLK buffer, under open input conditions, will maintain a defined output state and thus the Q outputs of the device will be in a defined state (Q = LOW). Note that if all of the inputs are left open the differential CLK input will be selected and the state of the Q outputs will be undefined. With the simultaneous switching characteristics and the tight skew specifications of the E211 the handling of the unused outputs becomes critical. To minimize the noise generated on the die all outputs should be terminated in pairs, ie. both the true and compliment outputs should be terminated even if only one of the outputs will be used in the system. With both complimentary pairs terminated the current in the VCC pins will remain essentially constant and thus inductance induced voltage glitches on VCC will not occur. VCC glitches will result in distorted output waveforms and degradations in the skew performance of the device. The package parasitics of the 28-lead PLCC cause the signals on a given pin to be influenced by signals on adjacent pins. The E211 is characterized and tested with all of the outputs switching, therefore the numbers in the data book are guaranteed only for this situation. If all of the outputs of the E211 are not needed and there is a desire to save power the unused output pairs can be left unterminated. Unterminated outputs can influence the propagation delay on adjacent pins by 15ps - 20ps. Therefore under these conditions this 15ps 20ps needs to be added to the overall skew of the device. Pins which are separated by a package corner are not considered adjacent pins in the context of propagation delay influence. Therefore as long as all of the outputs on a single side of the package are terminated the specification limits in the data sheet will apply.
E211 Q0 BACKPLANE Q8
E111 Q0
Q5
Q8
Figure 1. Standard E211 Application
Using the E211 in PECL Designs The E211 device can be utilized very effectively in designs utilizing only a +5V power supply. Since the internal switching reference levels are biased off of the VCC supply the input thresholds for the single-ended inputs will vary with VCC. As a result the single-ended inputs should be driven by a device on the same board as the E211. Driving these inputs across a backplane where significant differences between the VCC's of the transmitter and receiver can occur can lead to AC performance and/or significant noise margin degradations. Because the differential I/O does not use a switching reference, and due to the CMR range of the E211, even
MOTOROLA
2-4
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E211 MC100E211
APPLICATIONS INFORMATION
Differential versus Single-Ended Use As can be seen from the data sheet, to minimize the skew of the E211 the device must be used in the differential mode. In the single-ended mode the propagation delays are dependent on the relative position of the VBB switching reference. Any VBB offset from the center of the input swing will add delay to either the TPLH or TPHL and subtract delay from the other. This increase and decrease in delay will lead to an increase in the duty cycle skew and thus part-to-part skew. The within-device skew will be independent of the VBB and therefore will be the same regardless of whether the device is driven differentially or single-endedly. For applications where part-to-part skew or duty cycle skew are not important the advantages of single-ended clock distribution may lead to its use. Using single-ended interconnect will reduce the number of signal traces to be routed, but remember that all of the complimentary outputs still need to be terminated therefore there will be no reduction in the termination components required. To use the E211 with a single-ended input the arrangement pictured in Figure 2b should be used. If the input to the differential CLK inputs are AC coupled as pictured in Figure 2a the dependence on a centered VBB reference is removed. The situation pictured will ensure that the input is centered around the bias set by the VBB. As a result when AC coupled the AC specification limits for a differential input can be used. For more information on AC coupling please refer to the interfacing section of the design guide in the ECLinPS data book. Using the Enable Pins Both the common enable (CEN) and the individual enables (ENx) are synchronous to the CLK or SCLK input depending on which is selected. The active low signals are clocked into the enable flip flops on the negative edges of the E211 clock inputs. In this way the devices will only be disabled when the outputs are already in the LOW state. The internal propagation delays are such that the delay to the output through the distribution buffers is less than that through the enable flip flops. This will ensure that the disabling of the device will not slice any time off the clock pulse. On initial power up the enable flip flops will randomly attain a stable state, therefore precautions should be taken on initial power up to ensure the E211 is in the desired state.
IN 0.001F IN 50
0.01F
VBB
Figure 2a. AC Coupled Input
IN
IN
0.01F
VBB
Figure 2b. Single-Ended Input
ECLinPS and ECLinPS Lite DL140 -- Rev 4
2-5
MOTOROLA
MC10E211 MC100E211
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
0.007 (0.180) U T L -M
M
B -NY BRK
M
S
N
S S
0.007 (0.180)
T L -M
N
S
D Z -L-M-
W
28 1
D X VIEW D-D G1 0.010 (0.250)
S
V
T L -M
S
N
S
A Z R
0.007 (0.180) 0.007 (0.180)
M
T L -M T L -M
S
N N
S
H
S
0.007 (0.180)
M
T L -M
S
N
S
M
S
C
E G G1 0.010 (0.250)
S
K1 0.004 (0.100) J -TSEATING PLANE
K F VIEW S 0.007 (0.180)
M
VIEW S T L -M
S
T L -M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.410 0.430 0.040 --
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 10.42 10.92 1.02 --
MOTOROLA
2-6
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E211 MC100E211
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
ECLinPS and ECLinPS Lite DL140 -- Rev 4 2-7
*MC10E211/D*
MC10E211/D MOTOROLA

▲Up To Search▲

Price & Availability of MC10E211FN

	To Download MC10E211FN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .